Investigation of Self-Heating Effects in Vacuum Gate Dielectric Gate-all-Around Vertically Stacked Silicon Nanowire Field Effect Transistors

Abstract

The self-heating effects in vacuum gate dielectric gate-all-around field effect transistors (GAA FETs) with vertically stacked 4-nm silicon nanowire (SiNW) channels are investigated by 3-D TCAD simulation. The cross-sectional dimension-dependent thermal conductivity model of the SiNW is proposed for the precise numerical simulation of self-heating effects based on the temperature-dependent thermal conductivity of the bulk silicon. The thermal conductivity model which was verified by published data indicates that thermal conductivity of 4-nm SiNW is greatly reduced to below 10 W/mK due to the pronounced phonon boundary scattering. Simulation results shows that the vacuum gate dielectric devices undergo more severe self-heating effects than the solid gate dielectric GAA SiNW FETs, resulting in more serious performance degradation. Multiple heat sources generated by the three-stacked SiNWs make heat generation and diffusion more difficult. An effective method is proposed to suppress the self-heating effects by increasing the spacing of the gas gap within in a certain range and the around ambient gas pressure.