High performance horizontal gate-all-around silicon nanowire field-effect transistors

Abstract

Semiconducting nanowires have been pointed out as one of the most promising building blocks for submicron electrical applications. These nanometer materials open new opportunities in the area of post-planar traditional metal-oxide-semiconductor devices. Herein, we demonstrate a new technique to fabricate horizontally suspended silicon nanowires with gate-all-around field-effect transistors. We present the design, fabrication and electrical measurements of a high performance transistor with high on current density (~150 μA μm(-1)), high on/off current ratio (10(6)), low threshold voltage (~ - 0.4 V), low subthreshold slope (~100 mV /dec) and high transconductance (g(m) ~ 9.5 μS). These high performance characteristics were possible due to the tight electrostatic coupling of the surrounding gate, which significantly reduced the Schottky-barrier effective height, as was confirmed experimentally in this study.