FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders

Abstract

This paper describes the implementation of an 8-bit Vedic multiplier using fast adder enhanced in terms of propagation delay when compared with conventional multiplier.In our design of 8 bit Vedic multiplier using fast adder, we have utilized 8-bit barrel shifter which requires only one clock cycle for 'n' number of shifts.The design of 8 bit Vedic multiplier using barrel shifter is implemented and verified using FPGA and ISE Simulator.The core used here was implemented on Altera Cyclone® II 2C20 FPGA device software.The propagation delay between 8 bit Vedic multiplier using barrel shifter using barrel shifter and using fast adder comparison was extracted from the synthesis report and static timing report as well.The design which is implemented here could achieve propagation delay of 6.781ns using barrel shifter block in base selection module and multiplier of architecture used.In our project, we make a comparison between performance analysis of 8 bit Vedic multiplier using barrel shifter and using fast adder.