High-Speed Vedic Multiplier Implementation Using Memristive and Speculative Adders

Abstract

In ALU's, among accumulators and various other signal processing modules, the most significant operating block is multipliers. Due to the requirement of minimum delay, special importance is certain in designing faster multipliers. Among numerous multiplier designs, Vedic multipliers are ideal for their operational speed. Sixteen Vedic multiplication sutras are speed efficient in their way. The proposed "URDHVA TIRYAKBHYAM" is a technique which has been effective in terms of speed. Further, the performance of the Vedic multiplier is compared by employing different adders such as ripple carry adder, inexact speculative adder, IMPLY logic Memristive adder. The proposed Vedic multipliers improved in delay compared with the existing model. Parallel computation of partial products and summation is an added advantage in reducing the delay of the multiplier. Results of Vedic multiplier designs integrated with different adders are compared after simulating using the Xilinx Vivado tool.