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JOURNAL ARTICLE

FPGA implementation of high speed Vedic multiplier

Sheetal N. GadakhAmitkumar Khade

Year: 2016 Pages: 4 .-4 .
DOI: 10.1049/cp.2016.1144
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Keywords:
Field-programmable gate array Multiplier (economics) Computer science Embedded system

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0
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0.82
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Citation History

Topics

Low-power high-performance VLSI design
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Quantum-Dot Cellular Automata
Physical Sciences →  Computer Science →  Computational Theory and Mathematics
Evolutionary Algorithms and Applications
Physical Sciences →  Computer Science →  Artificial Intelligence

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