FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics.

Abstract

A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in general processors.This paper proposes the design of 8x8 bit Vedic multiplier based on vertical and crosswise structure of Ancient Indian Vedic Mathematics.The proposed architecture is for two 8-bit numbers, the multiplier and multiplicand each arc grouped as 4-bit numbers; so that it decomposes into 4x4 multiplication modules.This gives chance for modular design where smaller blocks can be used to design the bigger one.Further, the VHDL coding of Urdhava Tiryakbhyam sutra for 8x8 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool have been done.