FPGA Implementation of Novel High Speed Vedic Multiplier

Abstract

Now a day's almost all DSP and Communication applications require high speed processors.The speed of a processor is mainly given in terms of performance of ALU and in turn in terms of MAC unit.MAC (multiplier and accumulator unit) is the main arithmetic processing unit of ALU.The demand for high speed processing necessitates high speed multiplier architecture.In this paper, a novel high speed 8-bit Vedic Multiplier is proposed using the Ancient Indian Vedic Mathematics technique.It uses four 4X4 multipliers designed using Urdhwa Tiryagbhyam sutra for partial product generation.This stage is optimized in terms of delay and power by using novel high speed 4:2 compressor architecture.The partial product addition stage is accomplished by using three modified Ripple Carry Adders.Final result is just the Concatenation of specific output bits of Ripple Carry Adders.The coding of the proposed multiplier is done in VHDL and simulated using Xilinx ISE 14.7.The design is synthesized using Xilinx-XST.The design is implemented on FPGA (field programmable gate array) kit, Spartan-6 (XC6SLX45) series.The results presented in this paper are compared with 8-bit conventional multiplier architectures.The efficiency of proposed architecture is given in terms of reduced area, low critical path delay and low hardware complexity.Results shown in this paper proves that the proposed 8-bit multiplier is 1.11 times faster than the normal 8-bit Vedic multiplier.