Hardware coprocessor integration with NEORV32: characterization for efficient implementation of RISC-V-based AI SoCs

Unai Sainz-Estebanez; Unai Martinez-Corral; Koldo Basterretxea

doi:10.1109/dcis62603.2024.10769177

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Hardware coprocessor integration with NEORV32: characterization for efficient implementation of RISC-V-based AI SoCs

Unai Sainz-Estebanez Unai Martinez-Corral Koldo Basterretxea

Year: 2024 Pages: 1-6

DOI: 10.1109/dcis62603.2024.10769177

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Keywords:

Coprocessor Computer science Reduced instruction set computing Embedded system Characterization (materials science) Computer architecture System on a chip Computer hardware Instruction set

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Radiation Effects in Electronics

Physical Sciences → Engineering → Electrical and Electronic Engineering

Hardware coprocessor integration with NEORV32: characterization for efficient implementation of RISC-V-based AI SoCs

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