A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators

R. Vijayaraghavan; Ahmed Kamaleldin; Matthias Nickel; Diana Göhringer

doi:10.1109/ipdpsw66978.2025.00199

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JOURNAL ARTICLE

A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators

R. Vijayaraghavan Ahmed Kamaleldin Matthias Nickel Diana Göhringer

Year: 2025 Pages: 1221-1227

DOI: 10.1109/ipdpsw66978.2025.00199

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Keywords:

Coprocessor Computer science Operating system Embedded system Computer architecture Reduced instruction set computing Parallel computing Instruction set

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Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Advanced Data Storage Technologies

Physical Sciences → Computer Science → Computer Networks and Communications

A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators

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