Hardware Design of SM2 Coprocessor Based on RISC-V

Abstract

The algorithm SM2 is used as the Elliptic Curve Cryptography (ECC) standard in China, due to the complexity of its computational process, it faces the challenge of low implementation efficiency. In this paper, we present a hardware design of SM2 coprocessor based on RISC-V architecture. The coprocessor is designed with hardware/software co-design and utilizes an improved traditional binary expansion method to achieve parallel execution of point addition and point doubling operations, and hardware acceleration through custom instruction extensions to improve the efficiency of point multiplication computation in the prime and binary domains. After experimental verification on Xilinx ARTIX-7 FPGA, during the encryption and decryption processes, compared to the traditional software algorithm, the cycles and instructions are only 5.47% and 2.96% respectively. In terms of resource utilization, the coprocessor occupies a total of 6754 slice. The experimental results show that the remarkable advantages of our coprocessor in terms of processing speed and resource efficiency, providing a feasible solution for the software/hardware co-design of the SM2 algorithm.