Design and Implementation of SM4 Coprocessor Based on RISC-V

Abstract

A co-processor with SM4 algorithm is designed for information security hazards and the application of RISC-V processor and SM4 algorithm in the security field. The co-processor is designed with a cyclic iterative structure to save resources, while four extension instructions are customized and embedded in the C program using inline assembly to facilitate calls, and the SM4 algorithm is accelerated by hardware and software co-design with independent memory access channels. Finally, the co-processor is described and simulated at the behavioral level by hardware description language, and the co-processor-equipped Hummingbird E203 is deployed on AX7103 FPGA development board for synthesis and analysis. The comprehensive results show that the overall number of encryption and decryption instructions of the SM4 algorithm is reduced by 99.84% and the number of cycles is reduced by 99.62% after adopting the coprocessor, and the proposed design scheme can significantly improve the computing efficiency of the SM4 algorithm.