BCD (Bipolar - CMOS - DMOS) [1]–[5] products have been widely used as power management chips. Oxide punch through etching is an important process in the BCD flow, directly affecting silicon deposition, thereby affecting the grounding of the substrate. This layer requires a high Oxide / Silicon selectivity to prevent Silicon recess, as well as minimal consumption of the oxide liner for sidewall to prevent poly gap fill from generating void. This paper introduces an ultra-low temperature oxide etching method. Although the aspect ratio exceeds 4X:1, the sidewalls of the oxide liner are almost not consumed, and a high Oxide / Silicon selection ratio greater than 10X is achieved, perfectly meeting the requirements.
Vladimir JovanovićTomislav SuligojLis K. Nanver
Vladimir JovanovićTomislav SuligojLis K. Nanver
Yemin TangA SandoughsazKhalil Najafi