LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

Abstract

The energy-efficient computing-in-memory (CIM) architectures have drawn much attention as the increasing demands of neural networks. Several SRAM-based CIM architectures adopt a digital implementation, using the digital adder trees (ATs) to perform in-memory multiply-accumulate (MAC) operations. Compared with the analog-domain CIM, the digital CIM eliminates errors caused by analog circuits to achieve high accuracy. However, the digital AT still incurs much power/area overhead. This brief proposes a novel low-power AT solution by sparsity and approximate circuits co-design. Several sparsity modes are explored to perform approximate logic substitution of the full adder. Besides, fine-grain pruning algorithm and offline data rearrangement compensate for the accuracy loss incurred by approximation. The proposed approximation scheme achieves at least a 19.3% reduction in area and a 30.0% reduction in power consumption. The maximum inference accuracy of the LeNet model on MNIST dataset is slightly 0.06% lower than the baseline accuracy. On the retrained Vgg8 and Vgg16 models on Cifar-10 dataset, the proposed three approximation strategies incur at most 0.99% accuracy decreases.