DESIGN AND ANALYSIS OF ULTRA LOW POWER APPROXIMATE ADDER

Abstract

In modern high-performance computing systems, low power designs are essential to ensure reliability, minimize cooling costs and enable portability.The design of adders has a significant impact on the computing system speed and power dissipation.Despite approximate full adder circuits dissipate less power than conventional full adder, they can still have a significant impact on the overall circuit.This initiated the development of a new adiabatic approximate adder that leverages efficient charge recovery logic techniques to implement the full adder with minimal power dissipation and reduced delay.In this work an approximate full adder is designed using CMOS and adiabatic logic.Functional verification of the designed full adder is carried out using Cadence Virtuoso at 45nm technology node.The performance of the designed adiabatic approximate adder circuits are compared in terms of power dissipation and delay.The impact of supply voltage scaling on power dissipation is also analyzed.The power dissipation and delay results demonstrated that the effectiveness of the proposed adiabatic approximate adder.