BOOK-CHAPTER
Design of Error-Tolerant and Low-Power Approximate Full Adder
Ketki C. PathakAnand D. DarjiJignesh N. SarvaiyaZinal BhattAnjali GangadwalaShreya DiwanAzba Patel
Year: 2022 Lecture notes in electrical engineering Pages: 53-66 Publisher: Springer Science+Business Media
Keywords:
Adder Computer science Serial binary adder Computation Carry-save adder Power (physics) Logic synthesis Arithmetic Logic gate Algorithm Electronic engineering Computer engineering Mathematics Telecommunications Engineering
Metrics
0
Cited By
0.00
FWCI (Field Weighted Citation Impact)
11
Refs
0.18
Citation Normalized Percentile
Is in top 1%
Is in top 10%
Topics
Low-power high-performance VLSI design
Physical Sciences → Engineering → Electrical and Electronic Engineering
Quantum Computing Algorithms and Architecture
Physical Sciences → Computer Science → Artificial Intelligence
Advancements in Semiconductor Devices and Circuit Design
Physical Sciences → Engineering → Electrical and Electronic Engineering
Related Documents
JOURNAL ARTICLE
Low Power Approximate Multiplier Using Error Tolerant Adder
Year: 2020 Vol: 2 4 Pages: 298-299
JOURNAL ARTICLE
Low Power Multiplier Using Approximate Adder for Error Tolerant Applications
Hemanth, C.Sangeetha, R. G.Kademani, SagarAli, Meer Shahbaz
Journal: OPAL (Open@LaTrobe) (La Trobe University) Year: 2024
JOURNAL ARTICLE
Low Power Multiplier Using Approximate Adder for Error Tolerant Applications
C. HemanthR. G. SangeethaSagar KademaniMeer Shahbaz Ali
Journal: IETE Journal of Research Year: 2024 Vol: 71 (1)Pages: 292-302
JOURNAL ARTICLE
Design and Evaluation of Low Power Error Tolerant Adder
Rishikumar NAAnita Angeline AP Sasipriya
Year: 2023 Pages: 1-6