Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros

Ming-Guang Lin; Jiing-Ping Wang; Cheng-Yang Chang; An-Yeu Wu

doi:10.1109/aicas59952.2024.10595967

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Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros

Ming-Guang Lin Jiing-Ping Wang Cheng-Yang Chang An-Yeu Wu

Year: 2024 Pages: 362-366

DOI: 10.1109/aicas59952.2024.10595967

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Keywords:

Encoding (memory) Computer science Static random-access memory Macro Parallel computing Adder Computer architecture Tree (set theory) Random access memory Arithmetic Computer hardware Mathematics Artificial intelligence Programming language

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Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

VLSI and Analog Circuit Testing

Physical Sciences → Computer Science → Hardware and Architecture

VLSI and FPGA Design Techniques

Physical Sciences → Engineering → Electrical and Electronic Engineering

Approximate Adder Tree Design with Sparsity-Aware Encoding and In-Memory Swapping for SRAM-based Digital Compute-In-Memory Macros

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