Random telegraph signals in nanoscale vertical junctionless transistors with gate-all-around

Abstract

Abstract The role of a single defect on the performance of transistors must be better understood to improve the design and fabrication process of nanotransistors. Capacitive networks on 18 nm long gate junctionless (JL) vertical gate-all-around nanowire transistors are studied through random telegraph signals, with amplitudes as high as 60% for a single nanowire. Defect densities extracted from both JL and accumulation-mode transistors allows one to discuss number fluctuation-based noise models, questioning the significance of defect densities of less than one defect per nanodevice. It is shown that the consideration of an effective charge in the models solves this issue.