Reliability of Al₂O₃/In-Si-O-C Thin-Film Transistors with an Al₂O₃ Passivation Layer under Gate-Bias Stress

Abstract

Introduction Bottom-gate-type thin-film transistors (TFTs) have an advantage of active channel protection because the In-Si-O-C channel can be formed in the final fabrication process. However, it still remains a big issue of poor stability because the back-side surface of the In-Si-O-C channel is directly exposed to the environmental conditions, and some charges can easily occur due to the adsorption and desorption of gaseous species in air. To overcome this problem, the formation of a passivation layer is one promising process to protect the In-Si-O-C channel. Various inorganic materials, such as SiO 2 , Si 3 N 4 , and Al 2 O 3 , have been characterized as passivation layer. Al 2 O 3 layer deposited by atomic layer deposition (ALD) has exhibited excellent passivation capabilities for realizing the stable high-mobility oxide TFTs [1]. Al 2 O 3 passivation layers, which deposited by sputtering methods or the ALD process, generally have thicker film of over 20 nm, and a post-deposition annealing process is sometimes performed to improve the quality of the Al 2 O 3 layer [2, 3]. However, there is no report on the influences of growth temperature and thickness of the Al 2 O 3 passivation layer on the reliability for In-Si-O-C TFTs have been extensively studied. In this paper, we studied gate-bias stress instability of bottom-gate-type Al 2 O 3 /In-Si-O-C TFT with an Al 2 O 3 passivation layer, which deposited by low-temperature ALD at 50 °C. We also compared transistor properties of Al 2 O 3 gate insulator fabricated ALD and PE-ALD under gate-bias stress conditions. Experiment A 50-nm-thick Pt film as the gate electrode was deposited on Si substrate using an e-beam evaporator, followed by patterned by a photolithographic process. Next, a 30-nm-thick Al 2 O 3 gate insulator was deposited on the Pt gate electrode by ALD and PE-ALD at 300 °C using trimethylaluminium precursor and H 2 O oxidant gas and plasma oxygen gas, respectively, subsequently patterned using a dry etching process. A 10-nm-thick In-Si-O-C channel was formed on the Al 2 O 3 gate insulator through a stencil shadow mask at room temperature by co-sputtering using In 2 O 3 and SiC targets under an Ar/O 2 (11.0/1.0) atmosphere at 0.2 Pa. Post-deposition annealing was then performed at 300 °C for 60 min in air. An Au (100 nm)/Ti (10 nm) layer was deposited by the thermal evaporation method as the source and drain electrodes. Post-metal deposition annealing was performed at 250 °C for 10 min in O 3 . Finally, an Al 2 O 3 passivation layer was covered on the back-side surface of the In-Si-O-C channel by ALD at 50 °C using TMA and H 2 O gases. The thickness of the Al 2 O 3 passivation layer was varied to 2 nm (AlO-2), 5 nm (AlO-5), and 10 nm (AlO-10) by changing the number of ALD cycles. Results and Discussion Figure 1 shows a cross-sectional schematic of the fabricated bottom-gate-type Al 2 O 3 insulator/In-Si-O-C channel TFT with an Al 2 O 3 passivation layer. The channel length and width of the TFT used in this study were 350 μm and 1000 μm, respectively. Figure 2 shows the threshold voltage shift (Δ V th ) behavior of all devices as a function of the Al 2 O 3 passivation layer thickness under negative gate-bias stress (NBS) conditions. A significant negative V th shift appeared with the w/o device. The negative V th shift is generally recognized to cause hole charge trapping in the gate insulator and at the Al 2 O 3 insulator/In-Si-O-C channel interface. The holes are thought to be due to absorbed H 2 O molecules on the back-side of In-Si-O-C channel. The Δ V th of the AlO-2 and AlO-5 devices were slightly reduced compared to the w/o device. On the other hand, the Δ V th of the AlO-10 device were exhibited negligible small value, indicating that the thickness of Al 2 O 3 as a passivation layer is required to be 10 nm or more. Here, the Al 2 O 3 passivation layer which contains residual carbon impurities has low quality because of low-temperature ALD at 50 °C [4]. However, noted that this Al 2 O 3 film can effectively passivate the defects from absorbed H 2 O molecules. Low-temperature processable Al 2 O 3 passivation layer can be expected in flexible substrate. Conclusions We investigated gate-bias stress instability of bottom-gate-type Al 2 O 3 /In-Si-O-C TFTs with the Al 2 O 3 passivation layer, which deposited by low-temperature ALD at 50 °C. The AlO-10 device was exhibited negligible small Δ V th , which has no influence of H 2 O molecules. We found that the low-temperature fabricated Al 2 O 3 film is essential for suppressing influence of absorbed H 2 O molecules. Acknowledgment This work was supported by Grant-in-Aid for JSPS Fellows. References [1] S. Yang et al., Appl . Phys . Lett . 96 , 213511 (2010). [2] S-Y Huang et al., Surf . Coat . Technol . 231 , 117-121 (2013). [3] J-I. Park et al., J. Vac. Sci. Technol. B 35 , 4 (2017). [4] T. Nabatame et al., Vacuum and Surface Science 61 , 5 (2018). Figure 1