(Invited) Interface and Dielectric Engineering for High-Performance Top-Gated MoS₂ Field Effect Transistors

Abstract

In recent years, due to the intriguing electrical and optical characteristics, two dimensional layered materials such as MoS 2 have attracted tremendous research attention. However, until now, majority of the efforts have been focused on the integration of MoS 2 devices in the back- or dual-gated geometry due to the difficulty of compact and conformal top-gated dielectric deposition directly onto the 2-D channel for the realization of high-performance top-gated FETs. In order to integration in TFT circuit for practical application, top-gated FETs with high- k dielectric is necessary. In this regard, interface or dielectric engineering is an important step towards the practical implementation of MoS 2 devices with the optimized performance. Here, we explore the case of interface engineering by utilizing an ultrathin metallic oxide (MgO, Al 2 O 3 and Y 2 O 3 ) buffer layer inserted between the ALD-HfO 2 and MoS 2 channel in order to achieve conformal HfO 2 /MoS 2 interfaces with the minimal interface defect density. Exploiting these enhanced gate stack dielectrics, we attain the highest saturation current (526 μA/μm) of any MoS 2 transistor reported to date, which is comparable to the same scaled state-of-the-art Si MOSFETs. At the same time, these devices also exhibit the impressive room-temperature mobility (63.7 cm 2 /V·s), on/off current ratio (>10 8 ) and near-ideal sub-threshold slope ( SS = 65 mV/decade). Although Y 2 O 3 /HfO 2 /MoS 2 structure improves the device performance greatly, the degradation in mobility is unavoidable. We then further utilize BN as dielectric layer to improve the mobility of top-gated MoS 2 device. The mobility value is close to 100 cm 2 /V·s, Demonstration of all these suggests that the performance of few-layer MoS 2 FETs can reach near intrinsic limits at room temperature along with the proper interface engineering and propose future directions to improve electrical characteristics in layered semiconductors.