(Invited) Interface Engineering of High-k Dielectrics and Metal Contacts for High Performance Top-Gated MoS₂ FETs

Abstract

The 2D materials, in particular Transition Metals Di-chalcogenides (TMD), are potential candidates to scale CMOS technology beyond Silicon. The ability to deposit ultrathin TMD films, down to a mono-layer, offers excellent electrostatic control of the channel by the gate electrode. This enables aggressive scaling of the channel length of transistor, due to superior short channel performance. In particular, few layer Molybdinum Disulphide (MoS 2 ), with a bandgap comparable to Silicon, has emerged as a promising candidate to to enable continued transistors scaling. However, high performance and reliable gate dielectric and contact formation continues to be an open problem. Since the impurity doping strategies for MoS 2 are still not clear, the ohmic contact formation is limited by the nature of metal-semiconductor schottky contact. Despite the Fermi level pinning close to conduction band of MoS 2 , a low source/drain contact resistance value for NMOS transistor is limited by the surface state effects. The problem is exasperated due to large variations in contact resistance values within the wafer, possibly due to surface defects and stoichiometric variations. We demonstrate that appropriate surface preparation can drastically enhance the performance of ohmic contacts on MoS 2 . In particular, we present a surface-state engineering technique using sulfur treatment of MoS 2 before the contact formation. The transistors (L=W= ~1μm) are formed on exfoliated few layer MoS 2 flakes (5-7 nm thick). The flakes are treated with ammonium sulphide solution (NH 4 ) 2 S (Sigma Aldrich, 40% solution in H 2 O) for 5 min at a temperature of 50 °C, followed by De-ionized water rinse and N 2 blow-dry. Nickel (Ni) and Palladium (Pd) contacts are formed using lift-off process. Through extensive material and electrical characterization, we demonstrate that the sulfur treatment reduces to schottky barrier height by 81 meV (Ni) and 135 meV (Pd) due to stronger pinning of Fermi level. This in turn lowers the contact resistance by as much as 10 times with concomitant increase in mobility by a factor of 2. We demonstrate record drain current of 170μA/μm, with complete mitigation of contact resistance and hence drain current variability. Due to the inert basal plane of 2D materials, it is difficult nucleate the growth of dielectrics using CVD and/or ALD techniques, which are routinely used for high-k dielectric integration on Silicon. Although some techniques have been proposed to nucleate the dielectric growth on MoS 2 , the device performance is inferior due to interface defects. To circumvent this issue, we develop a very high performance HfO 2 thin film using electron beam evaporation. The O 2 flow rate is optimized during e-beam evaporation to achieve 30nm HfO 2 films with k=19 and EOT=6.1 nm. The interface trap density is estimated to be 8.7x10 11 /cm 2 , resulting in a very high field effect mobility value of 63 cm 2 /V-s. The HfO 2 gate oxide results in a very low leakage current of 7x10 -7 A/cm 2 . The top gated transistors fabricated with this dielectric yield one of the highest reported drain current value of 180 μA/μm, with near ideal subthreshold behaviour (60 to 75 mV/decade). We also utilize 30nm HfO 2 dielectric as a substrate to deposit MOS 2 flakes, instead of conventional 300nm SiO 2 substrate. Finally we demonstrate an NMOS inverter circuit using HfO 2 top-gated devices using a depletion mode NMOS transistor as a resistive load. The Inverter exhibits an output to input gain of about 9. Figure 1