Pipelined parallel multiplier implementation

Abstract

Two's complement pipelined array and Wallace/Dadda (1964, 1965) multipliers are designed using LSI Logic 1.0-micron array based logic devices. The overall complexity of the multipliers and delay per pipeline stage is compared for various operand bit lengths and pipeline stage sizes. In order to optimize complexity and delay, issues including fanout, individual gate size and delay, minimization of the number of bits passed between pipeline stages, and optimization of pipeline stage size are considered. Both scalar and vector modes of operation are optimized.< >