Novel pipelined serial/parallel multiplier

Djamel Ait-Boudaoud; M.K. Ibrahim; Barrie Hayes‐Gill

doi:10.1049/el:19900381

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JOURNAL ARTICLE

Novel pipelined serial/parallel multiplier

Djamel Ait-Boudaoud M.K. Ibrahim Barrie Hayes‐Gill

Year: 1990 Journal: Electronics Letters Vol: 26 (9)Pages: 582-583 Publisher: Institution of Engineering and Technology

DOI: 10.1049/el:19900381

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Abstract

A novel unidirectional pipelined serial/parallel multiplier (PSPM) is presented. This design has halves the initial delay and reduces the number of latches by 10% of the conventional structure. An area-time criteria is used to compare the new architecture with the old PSPM.

Keywords:

Multiplier (economics) Parallel computing Computer science

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Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Algorithms and Data Compression

Physical Sciences → Computer Science → Artificial Intelligence

Error Correcting Code Techniques

Physical Sciences → Computer Science → Computer Networks and Communications

Novel pipelined serial/parallel multiplier

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