The fully-serial pipelined multiplier

Andrew G. Shafer; Lyndsi R. Parker; Earl E. Swartzlander

doi:10.1109/acssc.2011.6190336

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The fully-serial pipelined multiplier

Andrew G. Shafer Lyndsi R. Parker Earl E. Swartzlander

Year: 2011 Pages: 1817-1822

DOI: 10.1109/acssc.2011.6190336

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Abstract

This paper presents a new multiplier design which is fully-serial and requires only 1.5N cycles to return a product. This design has been implemented for both unsigned and two's complement number systems. This design can be pipelined so that each additional multiplication only requires N cycles.

Keywords:

Multiplier (economics) Computer science Parallel computing Arithmetic Complement (music) Logic synthesis Multiplication (music) Logic gate Algorithm Mathematics

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Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Numerical Methods and Algorithms

Physical Sciences → Computer Science → Computational Theory and Mathematics

Digital Filter Design and Implementation

Physical Sciences → Computer Science → Signal Processing

The fully-serial pipelined multiplier

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