Pipelined serial/parallel multiplier with contraflowing data streams

Abstract

An improved architecture of the Muller pipeline serialparallel multiplier is presented. The proposed solution is based on the integration of two Muller cells into one. This modification has resulted in a reduction of the number of latches by 25% and an increase in the effectiveness of the architecture by eliminating interspersed zeros in the input data streams. An area×time criteria is used to compare the modified architecture with the Muller multiplier.