Phase-mode pipelined parallel multiplier

Abstract

We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.