Implementation of Pipelined Low Power Vedic Multiplier

Abstract

Pipelining is a technique used to reduce the energy consumption of a device. This, when used in combination with Vedic multipliers results in low-power systems with high speed. Vedic multipliers are based on the concept of Vedic mathematics, which is an ancient Indian method of computing mathematical operations. The algorithm of the system coded using Verilog Hardware Description Language is implemented on spartan 3E series of Field Programmable Gate Array (FPGA). The design shows a decrease in the power consumption and generates the results faster. The performance of the design is compared with that of few existing non-pipelined designs.