Pipelined architecture for vedic multiplier

Abstract

Vedic mathematics is derived from ancient mathematics which is the simplest form of multiplication of two numbers which is one among the 16 sutras. This Vedic mathematics improves the performance of the multiplier in terms of speed. By using this technique RTL coding for 4×4 Vedic multipliers with and without Pipelining, Simulation is performed in Modelsim and got the RTL schematic in Cadence (rc). The area, delay, power analysis of multiplier performed in Cadence (rc). The delay in the Pipelined architecture got reduced by 300ps.