Submicron GaAs microwave FET's with low parasitic gate and source resistances

S. Bandy; Yu Chai; Robert H. Chow; C. Nishimoto; G. Zdasiuk

doi:10.1109/edl.1983.25640

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Submicron GaAs microwave FET's with low parasitic gate and source resistances

S. Bandy Yu Chai Robert H. Chow C. Nishimoto G. Zdasiuk

Year: 1983 Journal: IEEE Electron Device Letters Vol: 4 (2)Pages: 42-44 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/edl.1983.25640

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Abstract

The substantial reduction in gate metallization resistance and improvement in performance of submicron-gate GaAs FET's has been achieved by employing a mushroom profile defined by electron-beam exposure. Using MBE growth of buffer, channel, and n+ contact layers, minimum noise figures of 1.0-1.1 dB have been demonstrated at 8 GHz, with associated gains of 13-14 dB.

Keywords:

Optoelectronics Materials science Parasitic element Microwave Contact resistance Gallium arsenide Noise figure Molecular beam epitaxy Logic gate Electrical engineering CMOS Layer (electronics) Nanotechnology Epitaxy Engineering Amplifier Telecommunications

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Semiconductor Quantum Structures and Devices

Physical Sciences → Physics and Astronomy → Atomic and Molecular Physics, and Optics

Advancements in Semiconductor Devices and Circuit Design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Radio Frequency Integrated Circuit Design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Submicron GaAs microwave FET's with low parasitic gate and source resistances

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