Low-power CMOS analog front-end for wireless communication

Abstract

A low-voltage low-power CMOS VLSI circuit for the main part of an analog front-end has been designed for wireless communication systems. Such analog circuits include an antialiasing filter, sample and hold circuit, and sixth order switched-resistor (SR) low-pass filter. The sample and hold circuit and the SR low-pass filter operate at 300 kHz. The effects of feedthrough and dynamic range in these circuits are taken into account. The proposed circuits are realized in a standard 0.35 /spl mu/m CMOS technology. The architecture and circuits described in this paper consumes about 3 mW from a /spl plusmn/1 V power supply.