Submicron CMOS technologies for low-noise analog front-end circuits

Abstract

This paper presents a study of the noise behavior of submicron CMOS transistors, in view of applications to high-density mixed-signal front-end systems for high-granularity detectors. The goal of this work is extending the knowledge in this field, presently focused on 0.25 /spl mu/m processes, to the following generation of CMOS technologies (with 0.18 /spl mu/m minimum gate length). The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/f noise contribution are experimentally characterized with noise measurements in a wide frequency range. The results of this analysis are used to establish low-noise design criteria concerning the choice of the polarity and of the channel dimensions (length and width) of the preamplifier input device in low-power operating conditions. A comparison with similar noise measurements on CMOS devices belonging to a 0.35 /spl mu/m process allows estimating the impact of gate-length scaling on both white and 1/f noise components. The noise radiation tolerance is also a key parameter for many front-end systems. It was evaluated by exposing the devices to high doses of ionizing radiation.