Silicon hybrid wafer-scale package technology

Wayne Johnson; J.L. Davidson; R.C. Jaeger; D.V. Kerns

doi:10.1109/jssc.1986.1052616

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Silicon hybrid wafer-scale package technology

Wayne Johnson J.L. Davidson R.C. Jaeger D.V. Kerns

Year: 1986 Journal: IEEE Journal of Solid-State Circuits Vol: 21 (5)Pages: 845-851 Publisher: Institute of Electrical and Electronics Engineers

DOI: 10.1109/jssc.1986.1052616

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Abstract

A wafer-scale packaging technology is discussed. Pretested IC chips are mounted in holes etched through silicon wafers. Chips are interconnected via the wafer using standard multilevel metallization processes. The packaging technology has the potential to provide the flexibility of hybrid techniques with the reliability and density of monolithic fabrication.

Keywords:

Wafer Materials science Wafer-scale integration Fabrication Reliability (semiconductor) Die preparation Flexibility (engineering) Chip-scale package Wafer-level packaging Silicon Wafer fabrication Scale (ratio) Electronic engineering Optoelectronics Wafer dicing Engineering

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3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Integrated Circuits and Semiconductor Failure Analysis

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Silicon hybrid wafer-scale package technology

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