Hybrid silicon wafer-scale packaging technology

Wayne Johnson; James W. Davidson; R. Jaeger; D.V. Kerns

doi:10.1109/isscc.1986.1156981

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JOURNAL ARTICLE

Hybrid silicon wafer-scale packaging technology

Wayne Johnson James W. Davidson R. Jaeger D.V. Kerns

Year: 1986 Pages: 166-167

DOI: 10.1109/isscc.1986.1156981

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Abstract

Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.

Keywords:

Wafer Wafer-scale integration Silicon Materials science Optoelectronics Wafer-level packaging Die preparation Hybrid silicon laser Scale (ratio) Chip-scale package Electronic engineering Engineering physics Engineering Wafer dicing Physics

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Topics

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Semiconductor Lasers and Optical Devices

Physical Sciences → Engineering → Electrical and Electronic Engineering

Hybrid silicon wafer-scale packaging technology

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