VLSI Implementation of an Efficient Pre-Trace Back Approach for Viterbi Algorithm

Abstract

This article focuses on trace back unit of Viterbi algorithm for constraint length K = 7. Conventional trace back unit comprises of three types of memory operations: decision bits write, trace back read & decode read whereas the pre-trace back approach exploits the inherent parallelism between the decision bits write & decode traceback operation. This approach results in reduction in latency & hardware. In this article, the implementation of trace back unit using pre-traceback approach is presented. The design has been implemented using high-level Verilog HDL and functionally verified by mapping on to Xilinx Virtex2P FPGA.