A VLSI design for a trace-back Viterbi decoder

T. K. Truong; M.T. Shih; I.S. Reed; E. Satorius

doi:10.1109/26.135732

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A VLSI design for a trace-back Viterbi decoder

T. K. Truong M.T. Shih I.S. Reed E. Satorius

Year: 1992 Journal: IEEE Transactions on Communications Vol: 40 (3)Pages: 616-624 Publisher: IEEE Communications Society

DOI: 10.1109/26.135732

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Abstract

A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.< >

Keywords:

Viterbi decoder Viterbi algorithm TRACE (psycholinguistics) Convolutional code Decoding methods Computer science Chip Sequential decoding Soft output Viterbi algorithm Very-large-scale integration Algorithm Embedded system Telecommunications

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Error Correcting Code Techniques

Physical Sciences → Computer Science → Computer Networks and Communications

Advanced Wireless Communication Techniques

Physical Sciences → Engineering → Electrical and Electronic Engineering

Cellular Automata and Applications

Physical Sciences → Computer Science → Computational Theory and Mathematics

A VLSI design for a trace-back Viterbi decoder

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