VLSI implementation of an area-efficient architecture for the Viterbi algorithm

Abstract

The Viterbi algorithm is widely used in communications and signal processing. Recently, several area-efficient architectures for this algorithm have been proposed. Area-efficient architectures trade speed for area by means of mapping the N states of the trellis describing the Viterbi algorithm to P processing elements, where N>P. In this paper a practical VLSI implementation of an area-efficient architecture to evaluate the Viterbi algorithm is presented. The architecture that has been implemented is composed of only two processing elements and the corresponding routing network to process, in different cycles, all the states of the trellis. The resulting architecture has been integrated in a chip using a 0.7 /spl mu/ CMOS technology, occupying an area of 9 mm/sup 2/.