Abstract

We present a novel 3D floorplanning algorithm with module splitting (3D-FMS). The proposed methodology allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. Our experimental results on MCNC and GSRC benchmarks show that 3D-FMS can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3D floorplanning algorithms, 3D-FMS reduces the system level total wirelength by 7.9%.

Keywords:
Floorplan Computer science Footprint Three-dimensional integrated circuit Integrated circuit layout Parallel computing Very-large-scale integration Placement Physical design Computer architecture Embedded system Integrated circuit Circuit design

Metrics

1
Cited By
0.27
FWCI (Field Weighted Citation Impact)
18
Refs
0.61
Citation Normalized Percentile
Is in top 1%
Is in top 10%

Topics

3D IC and TSV technologies
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
VLSI and FPGA Design Techniques
Physical Sciences →  Engineering →  Electrical and Electronic Engineering
Electronic Packaging and Soldering Technologies
Physical Sciences →  Engineering →  Electrical and Electronic Engineering

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