Power supply noise aware floorplanning and decoupling capacitance placement

Abstract

Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modules based on their spatial correlations in the floorplan. In this paper, power supply noise is, for the first time, incorporated into the cost function to determine the optimal floorplan in terms of area, wire length, and power supply noise. Compared to conventional floorplanning, which only considers area and wire length, power supply noise aware floorplanning can generate better floorplan both in terms of area and peak noise. The decoupling capacitance required by each module is also calculated and placed in the vicinity of the target module during the floorplanning process. Experimental results on MCNC benchmark circuits show that the peak power supply noise can be reduced by as much as 40% and both the total area and wire length are improved due to the reduced total decoupling capacitance budget gained from reduced power supply noise.