LCP for wafer-level chip-scale MEMS

Abstract

As defined in IPC/JEDEC J-STD-012, chip-scale packaging (CSP) refers to a packaging method where the final package area dimensions are no larger than 1.2 times the die. Wafer-level packaging refers to a method where a wafer containing multiple chips is processed for packaging before the individual dies have been sawn-cut for separation [1]. While chip-scale packages have been widely available in high-volume production, hermetic packaging at the wafer level is still either at the research stage or in low-volume manufacturing.