Wafer Level Chip Scale Packaging

Michael J. Topper

doi:10.1007/978-0-387-78219-5_16

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Wafer Level Chip Scale Packaging

Michael J. Topper

Year: 2008 Pages: 547-600

DOI: 10.1007/978-0-387-78219-5_16

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Keywords:

Wafer Chip-scale package Chip Wafer-scale integration Scale (ratio) Materials science Reliability engineering Computer science Embedded system Nanotechnology Engineering Physics Telecommunications

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Cited By

9.37

FWCI (Field Weighted Citation Impact)

Refs

0.98

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Copper Interconnects and Reliability

Physical Sciences → Materials Science → Electronic, Optical and Magnetic Materials

Wafer Level Chip Scale Packaging

Metrics

Citation History

Topics

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