Wafer Level Chip Scale Packaging

Michael J. Topper

doi:10.1007/978-3-319-45098-8_15

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Wafer Level Chip Scale Packaging

Michael J. Topper

Year: 2016 Pages: 627-695

DOI: 10.1007/978-3-319-45098-8_15

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Keywords:

Wafer-level packaging Wafer Materials science Wafer-scale integration Die preparation Miniaturization Chip Chip-scale package Mechanical engineering Manufacturing engineering Nanotechnology Engineering Electrical engineering Wafer dicing

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Cited By

1.86

FWCI (Field Weighted Citation Impact)

Refs

0.89

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Nanofabrication and Lithography Techniques

Physical Sciences → Engineering → Biomedical Engineering

Wafer Level Chip Scale Packaging

Metrics

Citation History

Topics

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