Wafer-Level Chip-Scale Packaging

Shichun Qu; Yong Liu

doi:10.1007/978-1-4939-1556-9

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Wafer-Level Chip-Scale Packaging

Shichun Qu Yong Liu

Year: 2014

DOI: 10.1007/978-1-4939-1556-9

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Keywords:

Chip-scale package Wafer Wafer-scale integration Reliability (semiconductor) Chip Wafer-level packaging Packaging engineering Scale (ratio) Power (physics) Reliability engineering Engineering Computer science Electrical engineering Mechanical engineering

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Cited By

0.73

FWCI (Field Weighted Citation Impact)

Refs

0.88

Citation Normalized Percentile

Is in top 1%

Is in top 10%

Citation History

Topics

3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Copper Interconnects and Reliability

Physical Sciences → Materials Science → Electronic, Optical and Magnetic Materials

Wafer-Level Chip-Scale Packaging

Metrics

Citation History

Topics

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