Gate-All-Around Silicon Nanowire Tunnel FETs for Low Power Applications

Abstract

In the era of portable electronic devices energy efficient integrated circuits (ICs) are highly demanded where the power consumption needs to be minimized by the reduction of the supply voltage . Digital circuits based on the complementary metal-oxide-semiconductor field effect transistors (MOSFETs), however, owns a physical limit of the minimum inverse sub-threshold slope (SS) of 60 mV/dec at room temperature. As consequence, the reduction of either leads to low ON-current or increases the OFF-current exponentially which in turn results in high power loss during idle state. Tunnel field effect transistors (TFETs) are proposed as a novel device concept with the potential to replace MOSFETs in low power applications. In comparison, TFETs can offer steeper transition between the OFF and the ON-state (SS<60 mV/dec) since the current transport mechanism relies on band-to-band tunneling. Within the framework of this thesis strained Si gate-all-around (GAA) nanowire TFETs are fabricated in order to achieve high tunneling currents and small SS. Very small nanowires, down to 5 nm in thickness and down to 15 nm in width, are surrounded by HfO2/TiN as high-k dielectric and metal gate to obtain optimal gate electrostatics for the device. Tilted ion implantation into the preformed thin epitaxial NiSi2 has been performed to benefit from dopant segregation that results in sharper doping profile for source and drain. Strained Si GAA nanowire p- and n-TFETs have been characterized indicating comparable current performance with 5 µA/µm at =0.5 V. SS below 60 mV/dec has been measured for the n-TFET for < 10-4 µA/µm at = 0.1 V at room temperate. However, most of the switching characteristics of the TFETs yield SS larger than the thermal limit. Trap-assisted tunneling is found to be the main root cause. High defect densities, especially in the source/channel interface, creates a parasitic current flow that obscure the SS < 60 mV/dec in the subthreshold region. Substantial characterization with pulsed - and temperature dependent DC measurements showed improved switching characteristics due to the reduction of the trap tunneling process.Complementary TFET (CTFET) inverter with and without ambipolar behavior are fabricated to demonstrate the applicability of the sSi GAA NW TFETs in logic circuits. By comparing the voltage transfer characteristics, both circuits indicate the basic inverter behavior but the ambipolar current conduction needs to be suppressed to obtain high static noise margins, larger voltage gain and - more importantly - to enable scaling. The suppression of the parasitic tunneling current has been achieved by using a gate-drain underlap with selective SiO2 spacer at the drain side. Robust CTFET inverter are achieved for the first time with large static noise margins. Based on the successful optimization of the inverter circuit, the world’s first half SRAMs with strained Si nanowire CTFET have been fabricated to explore the capability of TFETs for 6T-SRAM cells. Electrical measurements on cells with outward faced n-TFET access transistors have been performed to determine the static behavior. SRAM butterfly curves are created that allow the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the access transistor may lead to malfunctioning storage operation. This effect holds true even without the contribution of the ambipolar behavior but is justified by the inherent unidirectional current transport property of TFETs. Lowering the bit-line bias of the SRAM is found to mitigate this effect resulting in functional hold, read and write operation of the 6T-SRAM cell.