Performance Investigation of Gate-All-Around Nanowire Fets for Logic Applications

Abstract

In this paper, SiC and Si Nanowire Field Effect Transistors (NW-FETs) with SiO2 and HfO2 gate oxide materials are simulated in various gate oxide thicknesses and channel diameters. In order to study the performance of these transistors in logic applications, the effect of channel material and diameter and also oxide material and thickness changes on the important switching parameters like delay time (τd ), Power Delay Product (PDP) and Sub-threshold Swing (SS) are investigated. Results show that calculated parameters are sensitive to these changes. But the dependence of the parameters to the type of oxide material is higher in which by changing the oxide material to HfO2 τd decreases considerably. In addition, the optimum feature for the best switching speed is obtained. This study shows that SiC-NWFETs are comparable with Si-NWFETs in logic applications. Keywords: Delay Time, Nanowire Field Effect Transistor, Power Delay Product, Sub-threshold Swing, Switching Speed