The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

P. Jespers

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The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

P. Jespers

Year: 2009

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Keywords:

Electronic engineering Transistor Electronic circuit CMOS Slew rate Transconductance Computer science Amplifier Parasitic extraction Analogue electronics Bandwidth (computing) Operational amplifier Electrical engineering Engineering Voltage Telecommunications

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Advancements in Semiconductor Devices and Circuit Design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

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Citation History

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