Sizing low-voltage CMOS analog circuits

P.G.A. Jespers

doi:10.1109/icecs.2007.4511100

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Sizing low-voltage CMOS analog circuits

P.G.A. Jespers

Year: 2007 Vol: 31 Pages: 752-755

DOI: 10.1109/icecs.2007.4511100

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Abstract

A simple yet accurate MOS model intended for sizing CMOS analog circuits by means of the g _m /l _D methodology is proposed. The E.K.V.1 model is a good candidate but applies only to long channel transistors. Making the parameters functions of the source and drain voltage extends the model to short channel devices.

Keywords:

CMOS Sizing Transistor Electronic circuit Channel (broadcasting) Computer science Electronic engineering Analogue electronics Electrical engineering Voltage Engineering

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Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

Advancements in Semiconductor Devices and Circuit Design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

Sizing low-voltage CMOS analog circuits

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