High Performance Instruction-Data Level Parallelism Based Instruction Set Architecture in RISC-V

Giorgio Israel; Mohamed Asan Basiri M

doi:10.1109/cict64037.2024.10899652

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High Performance Instruction-Data Level Parallelism Based Instruction Set Architecture in RISC-V

Giorgio Israel Mohamed Asan Basiri M

Year: 2024 Pages: 1-6

DOI: 10.1109/cict64037.2024.10899652

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Keywords:

Computer science Instruction set Instruction-level parallelism Reduced instruction set computing Computer architecture Parallel computing Parallelism (grammar) Architecture Data parallelism Set (abstract data type) Programming language

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Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

High Performance Instruction-Data Level Parallelism Based Instruction Set Architecture in RISC-V

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