High Performance Data Level Parallelism based Instruction Set Architecture in RISC-V

Abstract

Performance is an indispensable factor in processes related to computer architecture. Data Level Parallelism (DLP) is useful to operate on multiple data streams under a single instruction multiple data (SIMD) instructions for improving the performance of the operations on the data. It has a great scope in computing huge chunks of data in an accelerated time, thus finding its applications in scientific calculators, big data processors, and fast computing applications. In this paper, we have proposed an instruction set architecture (ISA) in reduced instruction set computing (RISC)-V using GEM5 that provides faster computational results than the conventional instruction set. Karatsuba algorithm for the $64 \times 64$ bit multiplication can be carried out in several ways including thirty-two $16 \times 8$ bit multiplications, sixty-four $8 \times 8$ bit multiplications, sixteen $32 \times 8$ bit multiplications, and so on. When all the above computations are executed together there is a decrease of 71.55% latency with the proposed implementation in comparison to the conventional implementation. The latency of eight 8-bit additions is decreased by 22.31%, four $8\times 8$ multiplications is decreased by 11.34% and for one $8 \times 8$ bit multiplication and six 8 bit additions, latency is reduced by 19.98%.