An architecture for high instruction level parallelism

Abstract

High instruction level parallelism (ILP) can only be achieved when data flow and control flow constraints have been removed or reduced. Data flow constraints, not inherent in the original code, arise from lack of sufficient resources for initiation and execution of multiple instructions concurrently. Control flow, problems are caused by branches which force unpredictable changes in the sequential order of code execution. Removing these obstacles allows for the formation of larger basic blocks, resulting in higher ILP. The dataflow problems are reduced by increasing the number of functional units, registers, condition bits, by pipelining the functional units, and using nonblocking caches. The control flow problem is reduced by using techniques such as conditional execution, speculative execution, and software pipelining, leveraging hardware support. Thus, for high ILP, the processor architecture should include a very closely tied hardware and compiler architectures. An architecture that supports the above features, Software Scheduled SuperScalar, is presented in this paper.< >