Efficient Implementation of Fast Half Adder using 8T SRAM for In-Memory Computing Applications

Abstract

The recent development of data-intensive applications has resulted in crucial limitations in the conventional Von Neumann computing architecture. A highly significant advancement of in-memory computing has introduced an innovative approach to addressing this difficulty. This work presents a novel conceptualization of half-adder which is effectively incorporated into a memory array. The proposed design utilizes an 8T static random-access memory (SRAM) together with a multi-logic sense amplifier design. The architectural innovation outlined in the following description effectively utilizes the functions of three logic gates to carry out the essential activities of a half-adder. Significantly, this version of the half adder exhibits a significant reduction of 25% in time delay when compared to its existing designs which depended on a standard latch-type sense amplifier. The increased processing speed carries significant implications, particularly within the realm of managing contemporary data-intensive applications. Furthermore, this occurrence emphasizes the significant influence of memory-based computing within the domain of computing.