An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array

S Kavitha; Santosh Kumar Vishvakarma; Bhupendra Singh Reniwal

doi:10.1007/978-3-031-21514-8_23

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An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array

S Kavitha Santosh Kumar Vishvakarma Bhupendra Singh Reniwal

Year: 2022 Communications in computer and information science Pages: 262-274 Publisher: Springer Science+Business Media

DOI: 10.1007/978-3-031-21514-8_23

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Keywords:

Adder Static random-access memory Computer science CMOS Computer hardware 4-bit Von Neumann architecture Voltage Electronic engineering Parallel computing Electrical engineering Engineering

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Advanced Memory and Neural Computing

Physical Sciences → Engineering → Electrical and Electronic Engineering

Low-power high-performance VLSI design

Physical Sciences → Engineering → Electrical and Electronic Engineering

CCD and CMOS Imaging Sensors

Physical Sciences → Engineering → Electrical and Electronic Engineering

An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array

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